Based Verification
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Based Verification Training Providers and Trainers
CVC Infotech We offer trainings on VLSI Verification topics.
Trainings & Workshops
Verification Centric Course
* Comprehensive Functional Verification (CFV)
Language Course
* SystemVerilog for Design (SVD)
* SystemVerilog Assertions (SVA)
* SystemVerilog for Verification (SVTB)
* Property Specification Language (PSL, IEEE 1850)
* Essential e (IEEE 1647)
Methodology
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StellarIP ... on SystemVerilog Language for Verification , Assertion Based Verification ,Verilog Simulation with cadence IUS tool, OVM ( Open Verification Methodology), Specman-e language and eRM. (e Reuse Methodology).
The tools we use for training are Specman tool, Cadence IUS(NcSim), Cadence Simvision
Pre-Requisites for this course are B. E/ B. Tech or M. E/ M. Tech in Electronics.
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